Design of hardware IP is critical to the acceleration an application can achieve.  At BigZetta, we have a library of FPGA accelerated IPs for sorting, merging, compression/decompression etc. which can be plugged into an existing application. These IPs can be integrated into a C/C++ as well as Java application (through JNI layer). Our carefully designed sort/merge/codec algorithms can handle any amount of data and perform computations 10-30 times faster than the CPU. IPs are extensible to handle any kind of size, data complexity. These IPs have been integrated into most popular big data tools and their performance has been evaluated on machines running on-prem or on cloud. The speed (and cost savings) are independent of choice of machines as the IPs provide similar speed-ups across variety of machines and FPGAs.